1. Field of the Invention
The present invention relates to a data output processor to be used when forming a conductive layer by an electrolytic plating in a layer formed with a plurality of recesses or trenches, and to a method of manufacturing a semiconductor device including the conductive layer formed by the electrolytic plating.
2. Description of the Related Art
In the field of a semiconductor device including a copper interconnect, the progressive micronization of an interconnect pattern resultant from the downscaling of the design rule has provoked an increasing demand for a better filling performance of a via and a trench in a copper plating process. Concurrently, reduction in thickness of a film to be deposited is also being required in all the design rules, for reducing a wafer diffusion cost and improving a production capacity. Accordingly, these two types of requirements have to be satisfied, in a copper (hereinafter designated by Cu) plating process.
In this respect, JP-A Laid-open patent publication No.2003-277985 discloses a plating process that causes a bottom-up growth in which a plated layer located at a bottom portion of a trench or a recess can predominantly grow, to cope with the micronization of a via or a trench.
However, forming a plated layer by the bottom-up growth process in a fine trench, a thicker film is finally formed on the trench than a plane region, which is called an overplating phenomenon. This leads to another drawback that a film thickness of region other than where the thicker film is formed becomes too thin. For example, when a fine pattern and a pattern including a wide interconnect coexist in a same layer, a thicker layer is formed on the fine pattern, while a layer formed on the wide interconnect often becomes so thin that the wide interconnect trench is not completely filled. Accordingly, normally a Cu plating thickness has to be set with a sufficient positive allowance, so as to completely fill in the wide interconnect trench. This inevitably leads to a lowered productivity in the Cu plating process. Besides, since an excessively thick plated layer is formed on the fine pattern, an increase of Cu-CMP (chemical mechanical polishing) slurry cost and the like raises an overall diffusion cost.
Further, although an additive called a leveller may be employed for restraining such overplating phenomenon, this causes various problems such as an additional cost increase from consumption and administration of the leveller, emergence of a void in a grain triple point after annealing, degradation of filling performance, and so on.